According to sources familiar with the matter, TSMC is developing an advanced chip packaging technology known as CoPoS, which stands for Chip-on-Panel-on-Structure. This innovative method employs a glass material that serves as a temporary carrier and is integrated into a final substrate featuring a three-layer sandwich structure.
TSMC is expected to commence mass production of chips utilizing CoPoS by the end of 2028. This new technology is anticipated to lower manufacturing costs while simultaneously enhancing performance.
Notably, Nvidia's Feynman AI chipset will be the first to adopt CoPoS technology, as this next-generation packaging is primarily designed for artificial intelligence and high-performance computing chips.
Should CoPoS prove to be transformative, it will reinforce TSMC's dominant position in the chip manufacturing sector and compel competing firms to explore alternative technologies.
